1. Field of the Invention
This invention relates in general to integrated circuits and in particular to integrated circuits in complementary circuit technology comprising at least two MIS field effect transistors of different channel types wherein the first is mounted in a doped semiconductor body of a first conductivity type and the second is mounted in a tub-shaped semiconductor body of a second conductivity type mounted in the semiconductor body.
2. Description of the Prior Art
In integrated circuits of the complementary circuit technology wherein two field effect transistors of different channel types with the first one mounted in a doped semiconductor body of a first conductivity type and the second mounted in a tub-shaped semiconductor body of a second conductivity type and wherein the semiconductor body 2 of the second conductivity type is electrically connected to a supply voltage and the first field effect transistor is provided with a source terminal which lies at a reference potential there is a difficulty in that four successive semiconductor layers of alternating conductivity type are generally present between a terminal of a field effect transistor of the first channel type which is mounted in the tub-shaped semiconductor region and a terminal of a field effect transistor of the second channel type which is mounted outside of this zone such that the one connecting region of the first transistor forms the first semiconductor layer and the tub-shaped semiconductor region forms the second with the semiconductor body forming the third and the one connecting region of the second transistor forming the first semiconductor layer. When an overvoltage which exceeds the supply voltage by a specific amount, as for example 500 mV, occurs on the mentioned terminal of the transistor of the first channel type, the pn-junction between the first and second semiconductor layers can be positively biased to a degree such that a current path occcurs between the transistor terminals and this current path is attributable to a parasitic thyristor effect (latchup) within the four layer structure. This current path will also remain in effect after the decay of the overvoltage and can thermally overload the integrated circuit.